IMX53CEC datasheet(124/204 Pages) FREESCALE

124 / 204 page

i.MX53xD Applications Processors for Consumer Products, Rev. 2

124

Freescale Semiconductor

Electrical Characteristics

4.7.15

SPDIF Timing Parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 81 and Figures , show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format

(SPDIF), including the timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing

of the modulating Tx clock (STCLK) for SPDIF in Tx mode.

SJ9

TMS, TDI data hold time

—

SJ10

TCK low to TDO data valid

—

SJ11

TCK low to TDO high impedance

—

SJ12

TRST assert time

100

—

SJ13

TRST set-up time to TCK low

—

1 T

DC = target frequency of SJC

2 V

M = mid-point voltage

Table 81. SPDIF Timing Parameters

Characteristics

Symbol

Timing Parameter Range

Units

Min

Max

SPDIFIN Skew: asynchronous inputs, no specs apply

—

0.7

SPDIFOUT output (Load = 50pf)

•Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

SPDIFOUT1 output (Load = 30pf)

•Skew

• Transition rising

• Transition falling

—

1.5

13.6

18.0

Modulating Rx clock (SRCK) period

srckp

40.0

—

SRCK high period

srckph

16.0

—

SRCK low period

srckpl

16.0

—

Modulating Tx clock (STCLK) period

stclkp

40.0

—

STCLK high period

stclkph

16.0

—

STCLK low period

stclkpl

16.0

—

Table 80. JTAG Timing (continued)

Parameter1,2

All Frequencies

Unit

Min

Max

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