IMX53CEC datasheet(117/204 Pages) FREESCALE

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Electrical Characteristics

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

117

4.7.12.3

UDMA Output Timing

Figure 71 shows timing when the UDMA out transfer starts, Figure 72 shows timing when the UDMA out

host terminates transfer, Figure 73 shows timing when the UDMA out device terminates transfer, and

Table 76 lists the timing parameters for UDMA out burst.

Figure 71. UDMA Out Transfer Starts Timing Diagram

tcyc

tc1

(tcyc – tskew) > T

T big enough

trp

trp (min) = time_rp

× T – (tskew1 + tskew2 + tskew6)

time_rp

—tx11

(time_rp

× T) – (tco + tsu + 3T + 2 ×tbuf + 2×tcable2) > trfs (drive)

time_rp

tmli

tmli1

tmli1 (min) = (time_mlix + 0.4)

× T

time_mlix

tzah

tzah (min) = (time_zah + 0.4)

× T

time_zah

tdzfs

tdzfs = (time_dzfs

× T) – (tskew1 + tskew2)

time_dzfs

tcvh

tcvh = (time_cvh

×T) – (tskew1 + tskew2)

time_cvh

—ton

toff2

ton = time_on

× T – tskew1

toff = time_off

× T – tskew1

—

1 There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last

active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.

2 Make ton and toff big enough to avoid bus contention.

Table 75. UDMA in Burst Timing Parameters (continued)

ATA

Parameter

from

Figure 68,

Figure 69,

Figure 70

Description

Controlling Variable

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