ADSP-21469KBZ-ENG2 datasheet(21/56 Pages) AD

21 / 56 page

ADSP-21469/ADSP-21469W

Preliminary Technical Data

Rev. PrB

Page 21 of 56

November 2008

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 13.

Table 13. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

tRSTVDD

RESET Low Before VDDEXT or VDDDDR2 On

tEVDD-DDR2VDD

VDD_EXT on Before VDD_DDR2

TBD

tDDR2VDD_IVDD

VDD_DDR2 on Before VDD_INT

TBD

tCLKVDD

CLKIN Valid After VDD_INT Valid

200

tCLKRST

CLKIN Valid Before RESET Deasserted

102

tPLLRST

PLL Control Setup Before RESET Deasserted

203

Switching Characteristic

tCORERST

Core Reset Deasserted After RESET Deasserted

4096

× t

CK + 2 × tCCLK

4, 5

1 Valid VDD_INT assumes that the supply is fully ramped to its 1 volt rail. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design

of the power supply subsystem.

2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time. Assume

a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

3 Based on CLKIN cycles.

4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

5 The 4096 cycle count depends on tSRST specification in Table 15. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

Figure 4. Power-Up Sequencing

CLKIN

RESET

tRSTVDD

RESETOUT

VDDINT

VDDEXT

tPLLRST

tCLKRST

tCLKVDD

EVDD-DDR2V D D

CLK_CFG 1-0

tCORERST

VDD_DDR2

DD R2V DD_ IVDD

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