ADSP-21469KBZ-ENG2 datasheet(46/56 Pages) AD

46 / 56 page

Rev. PrB

Page 46 of 56

November 2008

ADSP-21469/ADSP-21469W

Preliminary Technical Data

SPI Interface—Slave

Table 43. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

tSPICLKS

Serial Clock Cycle

TBD

tSPICHS

Serial Clock High Period

TBD

tSPICLS

Serial Clock Low Period

TBD

tSDSCO

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

TBD

tHDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

TBD

tSSPIDS

Data Input Valid to SPICLK edge (Data Input Set-up Time)

TBD

tHSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid

TBD

tSDPPW

SPIDS Deassertion Pulse Width (CPHASE=0)

TBD

Switching Characteristics

tDSOE

SPIDS Assertion to Data Out Active

TBD

tDSDHI

SPIDS Deassertion to Data High Impedance

TBD

tDDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time)

TBD

tHDSPIDS

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

TBD

tDSOV

SPIDS Assertion to Data Out Valid (CPHAS E = 0)

TBD

Figure 35. SPI Slave Timing

tHSPIDS

tDDSPIDS

tDSDHI

LSB

MSB

MSBVALID

tDSOE

tDDSPIDS

tHDSPIDS

MISO

(OUTPUT)

MOSI

(INPUT)

tSSPIDS

SPIDS

(INPUT)

SPICLK

(CP = 0)

(INPUT)

SPICLK

(CP = 1)

(INPUT)

tSDSCO

tSPIC HS

tSPICLS

tSPICLKS

tHDS

tSPICHS

tSSPIDS

tHSPIDS

tDSDHI

LSBVALID

MSB

MSBVALID

tDDSPIDS

MISO

(OUTPUT)

MOSI

(INPUT)

tSSPIDS

LSBVALID

LSB

CPHASE= 1

CPHASE= 0

tSDPPW

tDSOV

tHDSPIDS

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