ADSP-21469KBZ-ENG2 datasheet(43/56 Pages) AD

43 / 56 page

ADSP-21469/ADSP-21469W

Preliminary Technical Data

Rev. PrB

Page 43 of 56

November 2008

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given

in Table 39. Input signals (SCLK, FS, SDATA) are routed to the

DAI_P20–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DAI_P20–1 pins.

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter has an oversampling clock. This TxCLK

input is divided down to generate the biphase clock.

Table 39. S/PDIF Transmitter Input Data Timing

Parameter

Min

Max

Unit

Timing Requirements

tSISFS

FS Setup Before SCLK Rising Edge

TBD

tSIHFS

FS Hold After SCLK Rising Edge

TBD

tSISD

SData Setup Before SCLK Rising Edge

TBD

tSIHD

SData Hold After SCLK Rising Edge

TBD

tSITXCLKW

Transmit Clock Width

TBD

tSITXCLK

Transmit Clock Period

TBD

tSISCLKW

Clock Width

TBD

tSISCLK

Clock Period

TBD

1 AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 32. S/PDIF Transmitter Input Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

SAMPLE EDGE

tSISD

tSISFS

tSISCLKW

DAI_P20-1

(SDATA)

DAI_P20-1

(TXCLK)

tSIHD

tSIHFS

tSITXCLKW

tSITXCLK

tSISCLK

Table 40. Over Sampling Clock (TxCLK) Switching Characteristics

Parameter

Min

Max

Unit

TxCLK Frequency for TxCLK = 384 × FS

TBD

MHz

TxCLK Frequency for TxCLK = 256 × FS

TBD

MHz

Frame Rate

TBD

kHz

ADSP-21469KBZ-ENG2 bảng dữ liệu(PDF) 43 Page - Analog Devices

ADSP-21469KBZ-ENG2 bảng dữ liệu(HTML) 43 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

bảng dữ liệu tải về

Link URL