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ADSP-21469KBZ-ENG2 bảng dữ liệu(PDF) 1 Page - Analog Devices

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Giải thích chi tiết về linh kiện  SHARC Processor material that is subject to change without notice
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ADSP-21469KBZ-ENG2 bảng dữ liệu(HTML) 1 Page - Analog Devices

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Preliminary Technical Data
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC Processor
ADSP-21469/ADSP-21469W
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.3113
©2008 Analog Devices, Inc. All rights reserved.
SUMMARY
Note: This datasheet is preliminary. This document contains
material that is subject to change without notice.
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—5 Mbits of on-chip RAM
Code compatible with all other members of the SHARC family
The ADSP-21469 is available with a 450 MHz core instruction
rate with unique audiocentric peripherals such as the digi-
tal applications interface, serial ports, precision clock
generators, S/PDIF transceiver, asynchronous sample rate
converters, input data port, and more.
For complete ordering information, see Ordering Guide on
Page 56.
Figure 1. Functional Block Diagram
16
DDR2 DRAM
CONTROLLER
7
3
DATA
EXTERNAL PORT
SPI PORT (2)
GP TIMERS (2)
UART
DIGITAL PERIPHERAL INTERFACE
SERIAL PORTS (8)
INPUT DATA PORT/
PDAP
DIGITAL APPLICATIONS INTERFACE
IOD(32)
ADDR
DATA
IOA(19)
PM DATA BUS
DM DATA BUS
32
PM ADDRESS BUS
DM ADDRESS BUS
64
PX REGISTER
PROCESSING
ELEMENT
(PEY)
PROCESSING
ELEMENT
(PEX)
TIMER
INSTRUCTION
CACHE
32
x 48-BIT
DAG1
CORE PROCESSOR
PROGRAM
SEQUENCER
IOP REGISTER CONTROL
STATUS, & DATA BUFFERS
DAG2
8
x 4 x 32
I/O PROCESSOR
ASRC
GPIO
64
32
PRECISION CLOCK
GENERATORS (4)
TWO WIRE
INTERFACE
32
48
S/PDIF (RX/TX)
PLL
THERMAL
DIODE
19
GPIO
IRQ/FLAGS
LINK
PORTS
20
FLAGS
JTAG TEST & EMULATION
PWM
DAI PINS (20)
DPI PINS (14)
DDR2 CONTROL
24
ADDRESS
DATA
ADDRESS
8
DMA
ARBITER
8
x 4 x 32
5M BIT RAM
ASYNCHRONOUS
MEMORY
INTERFACE
(AMI)
4
S
AMI CONTROL
4 BLOCKS OF
ON-CHIP MEMORY
20
14
FFT
FIR
IIR
ACCELERATORS


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