ADSP-21469KBZ-ENG2 datasheet(45/56 Pages) AD

45 / 56 page

ADSP-21469/ADSP-21469W

Preliminary Technical Data

Rev. PrB

Page 45 of 56

November 2008

SPI Interface—Master

The ADSP-21469 contains two SPI ports. Both primary and sec-

ondary are available through DPI only. The timing provided in

Table 42 and Table 43 applies to both.

Table 42. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

tSSPIDM

Data Input Valid To SPICLK Edge (Data Input Setup Time)

TBD

tHSPIDM

SPICLK Last Sampling Edge To Data Input Not Valid

TBD

Switching Characteristics

tSPICLKM

Serial Clock Cycle

TBD

tSPICHM

Serial Clock High Period

TBD

tSPICLM

Serial Clock Low Period

TBD

tDDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time)

TBD

tHDSPIDM

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

TBD

tSDSCIM

FLAG3–0IN (SPI device select) Low to First SPICLK Edge

TBD

tHDSM

Last SPICLK Edge to FLAG3–0IN High

TBD

tSPITDM

Sequential Transfer Delay

TBD

Figure 34. SPI Master Timing

LSB

VALID

MSB

VALID

tSSPIDM

tHSPIDM

tHDSPIDM

LSB

MSB

tHSPIDM

tDDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

FLAG3

-0

(OUTPUT)

SPICLK

(CP = 0)

(OUTPUT)

SPICLK

(CP = 1)

(OUTPUT)

tSPICHM

tSPICLM

tSPICLKM

tSPICHM

tHDSM

tSPITDM

tHDSPIDM

LSB

VALID

LSB

MSB

VALID

tHSPIDM

tDDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

tSSPIDM

CPHASE= 1

CPHASE= 0

tSDSCIM

tSSPIDM

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