ADSP-21469KBZ-ENG2 datasheet(50/56 Pages) AD

50 / 56 page

Rev. PrB

Page 50 of 56

November 2008

ADSP-21469/ADSP-21469W

Preliminary Technical Data

OUTPUT DRIVE CURRENTS

Figure 39 shows typical I-V characteristics for the output driv-

ers of the ADSP-21469. The curves represent the current drive

capability of the output drivers as a function of output voltage.

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 15 on Page 23 through Table 46 on Page 49. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 40.

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 41. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 40). Figure 44 shows graphically

how output delays and holds vary with load capacitance. The

graphs of Figure 42, Figure 43, and Figure 44 may not be linear

outside the ranges shown for Typical Output Delay vs. Load

Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

Figure 39. ADSP-21469 Typical Drive at Junction Temperature

Figure 40. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

100

250

200

150

TBD

ZO = 50

(impedance)

TD = 4.04

1.18 ns

2pF

TESTER PIN ELECTRONICS

0.5pF

400

4pF

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

VLOAD

DUT

OUTPUT

Figure 41. Voltage Reference Levels for AC Measurements

Figure 42. Typical Output Rise/Fall Time (20% to 80%,

VDD_EXT = Max)

Figure 43. Typical Output Rise/Fall Time (20% to 80%,

VDD_EXT = Min)

INPUT

OUTPUT

1.5V

100

250

200

150

TBD

100

250

200

150

TBD

ADSP-21469KBZ-ENG2 bảng dữ liệu(PDF) 50 Page - Analog Devices

ADSP-21469KBZ-ENG2 bảng dữ liệu(HTML) 50 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

bảng dữ liệu tải về

Link URL