PCIMX258CJM4A datasheet(108/144 Pages) FREESCALE

108 / 144 page

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

108

Freescale Semiconductor

Note:

• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting

the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables figures.

• All timings are on pads when SSI is being used for data transfer.

• ”Tx” and “Rx” refer, respectively, to the transmit and receive sections of the SSI.

• For internal frame sync operation using external clock, the FS timing is the same as that of Tx data (for example, during AC97

mode of operation).

Table 81. SSI Transmitter Timing with External Clock

Parameter

Min.

Max.

Unit

External Clock Operation

SS22

(Tx/Rx) CK clock period

81.4

—

SS23

(Tx/Rx) CK clock high period

36.0

—

SS24

(Tx/Rx) CK clock rise time

—

6.0

SS25

(Tx/Rx) CK clock low period

36.0

—

SS26

(Tx/Rx) CK clock fall time

—

6.0

SS27

FS (bl) low/ high setup before (Tx) CK falling

–10.0

15.0

SS29

FS (bl) low/ high setup before (Tx) CK falling

10.0

—

SS31

FS (wl) low/ high setup before (Tx) CK falling

–10.0

15.0

SS33

FS (wl) low/ high setup before (Tx) CK falling

10.0

—

SS37

(Tx) CK high to STXD valid from high impedance

—

15.0

SS38

(Tx) CK high to STXD high/low

—

15.0

SS39

(Tx) CK high to STXD high impedance

—

15.0

Synchronous External Clock Operation

SS44

SRXD setup before (Tx) CK falling

10.0

—

SS45

SRXD hold after (Tx) CK falling

2.0

—

SS46

SRXD rise/fall time

—

6.0

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