PCIMX258CJM4A datasheet(97/144 Pages) FREESCALE

97 / 144 page

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

3.7.14.1

SIM Reset Sequences

SIM cards may have internal reset, or active low reset. The following subset describes the reset sequences

in these two cases.

3.7.14.1.1

SIM Cards with Internal Reset

Figure 69 shows the reset sequence for SIM cards with internal reset. The reset sequence comprises the

following steps:

•

After power-up, the clock signal is enabled on SIMx_CLKy (time T0)

•

After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted.

•

The card must send a response on SIMx_DATAy_RX_TX acknowledging the reset between

400–40000 clock cycles after T0.

Figure 69. Internal Reset Card Reset Sequence

Table 73 defines the general timing requirements for the SIM interface.

3.7.14.1.2

SIM Cards with Active Low Reset

Figure 70 shows the reset sequence for SIM cards with active low reset. The reset sequence comprises the

following steps:

•

After power-up, the clock signal is enabled on SIMx_CLKy (time T0)

•

After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted.

•SIMx_RSTy must remain low for at least 40,000 clock cycles after T0 (no response is to be

received on RX during those 40,000 clock cycles)

•SIMx_RSTy is asserted (at time T1)

•SIMx_RSTy must remain asserted for at least 40,000 clock cycles after T1, and a response must be

received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1.

Table 73. Timing Specifications, Internal Reset Card Reset Sequence

Ref No.

Min.

Max.

Units

—

200

clk cycles

400

40,000

clk cycles

SIMn_SVENm

SIMx_CLKy

SIMx_DATAy_RX_TX

RESPONSE

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