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PCIMX258CJM4A bảng dữ liệu(PDF) 47 Page - Freescale Semiconductor, Inc

tên linh kiện PCIMX258CJM4A
Giải thích chi tiết về linh kiện  i.MX25 Applications Processor for Consumer and Industrial Products
PDF  144 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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PCIMX258CJM4A bảng dữ liệu(HTML) 47 Page - Freescale Semiconductor, Inc

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3
Freescale Semiconductor
47
3.7.2.2
Multiword DMA (MDMA) Mode Timing
Figure 13 and Figure 14 show the timing for MDMA read and write modes, respectively.
Figure 13. MDMA Read Mode Timing
Figure 14. MDMA Write Mode Timing
To meet timing requirements, a number of timing parameters must be controlled. See Table 36 for details
on timing parameters for MDMA read and write modes.
Table 36. Timing Parameters for MDMA Read and Write Modes
ATA
Parameter
MDMA Read1
and Write2
Timing
Parameters
Relation
Adjustable
Parameter(s)
tm, ti
tm
tm(min.) = ti(min.) = time_m
× T – (tskew1 + tskew2 + tskew5)
time_m
td
td, td1
td1(min.) = td(min.) = time_d
× T – (tskew1 + tskew2 + tskew6)
time_d
tk
tk
tk(min.) = time_k
× T – (tskew1 + tskew2 + tskew6)
time_k
t0
—
t0(min.) = (time_d + time_k)
× T
time_d, time_k
tg(read)
tgr
tgr(min.–read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
tgr(min.–drive) = td – te(drive)
time_d
tf(read)
tfr
tfr(min.–drive) =0 k
—
tg(write)
—
tg(min.–write) = time_d
× T –(tskew1 + tskew2 + tskew5)
time_d
ADDR
(See note 1)
DIOR
READ Data(15:0)
DMARQ
DMACK
tm
td
tk
tkjn
tgr
tfr
tk1
te
ADDR
(See note 1)
DIOW
Write Data(15:0)
DMARQ
DMACK
tkjn
tk1
buffer_en
tm ton td1
tk
td
toff



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