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PCIMX258CJM4A bảng dữ liệu(PDF) 106 Page - Freescale Semiconductor, Inc

tên linh kiện PCIMX258CJM4A
Giải thích chi tiết về linh kiện  i.MX25 Applications Processor for Consumer and Industrial Products
PDF  144 Pages
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PCIMX258CJM4A bảng dữ liệu(HTML) 106 Page - Freescale Semiconductor, Inc

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3
106
Freescale Semiconductor
3.7.17.2
SSI Receiver Timing with Internal Clock
Figure 79 shows the timing for the SSI receiver with internal clock. Table 80 describes the timing
parameters (SS1–SS51) shown in the figure.
Figure 79. SSI Receiver Internal Clock Timing Diagram
Table 80. SSI Receiver Timing with Internal Clock
ID
Parameter
Min.
Max.
Unit
Internal Clock Operation
SS1
(Tx/Rx) CK clock period
81.4
—
ns
SS2
(Tx/Rx) CK clock high period
36.0
—
ns
SS3
(Tx/Rx) CK clock rise time
—
6.0
ns
SS4
(Tx/Rx) CK clock low period
36.0
—
ns
SS5
(Tx/Rx) CK clock fall time
—
6.0
ns
SS7
(Rx) CK high to FS (bl) high
—
15.0
ns
SS9
(Rx) CK high to FS (bl) low
—
15.0
ns
SS11
(Rx) CK high to FS (wl) high
—
15.0
ns
SS13
(Rx) CK high to FS (wl) low
—
15.0
ns
SS20
SRXD setup time before (Rx) CK low
10.0
—
ns
SS21
SRXD hold time after (Rx) CK low
0.0
—
ns
Oversampling Clock Operation
SS47
Oversampling clock period
15.04
—
ns
SS50
SS48
AUDn_TXC
AUDn_TXFS (bl)
AUDn_TXFS (wl)
AUDn_RXD
AUDn_RXC
SS1
SS4
SS2
SS51
SS20
SS21
SS49
SS7
SS9
SS11
SS13
SS47
(Output)
(Output)
(Output)
(Input)
(Output)
SS3
SS5



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