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PCIMX258CJM4A bảng dữ liệu(PDF) 112 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A bảng dữ liệu(HTML) 112 Page - Freescale Semiconductor, Inc |
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112 / 144 page ![]() i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 112 Freescale Semiconductor Figure 82. Start-up Sequence The output data can be read from adcout11...adcout0, and is available tdata nanoseconds after the rising edge of eoc. The reset signal and the digital signals controlling the analog switches (ypsw, xpsw, ynsw, xnsw) are totally asynchronous. The following conditions are necessary to guarantee the correct operation of the ADC: • The input multiplexer selection (selin11…selin0) is stable during both the last clock cycle (14th) and the first clock cycle (1st). The best way to guarantee this is to make the input multiplexer selection during clock cycles 2 to 13. • The references are stable during clock cycle 1 to 13. The best way to guarantee this is to make the reference multiplexer selection (selrefp and selrefn) before issuing an soc pulse and changing it only after an eoc pulse has been acquired, during the last clock cycle (14). |
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