AD9148BPCZ datasheet(68/73 Pages) AD

68 / 73 page

AD9148

Preliminary Technical Data

Rev. PrA | Page 68 of 73

TEST ACCESS PORT

The AD9148 incorporates a test access port (TAP) and

boundary scan architecture. The TAP has four pins that provide

access into the device for performing the boundary scan testing:

•

TMS ,test mode select input

•

TCK , test clock input

•

TDI , test data input

•

TDO , test data output

The instruction register holds the current instruction used by the

TAP controller to decide what to do with the test signals that are

received. Most commonly, the content of the instruction register

defines to which of the data registers signals should be passed.

Table 26 shows the supported instructions, the instruction code,

and the data register selected. All instruction codes that are not

listed in Table 26 are reserved.

Table 26. Instruction Code Register Definition

TAP Instruction

Instruction Code

Data Register

Selected

EXTEST

00000

Boundary scan

IDCODE

00001

IDCODE

SAMPLE/PRELOAD

00010

Boundary scan

BYPASS

11111

Bypass

The boundary scan register is the main test register. It provides

the means for moving data from and to the device pins. The

bypass register is a single bit register that passes data from TDI

to TDO. The IDCODE register contains the ID code and

revision number for the device. This information allows the

device to be linked to its boundary scan description language

(BSDL) file. The file contains details of the boundary scan

configuration for the device.

The content of the 32-bit IDCODE register is 0x227E51CB.

The TAP controller is reset to an inactive state by the internal

power-on-reset. Figure 90 shows the basic timing diagram of

the controller signals.

tDSYS

tSSYS

tDTDO

tSTAP

tHTAP

tHSYS

tTCK

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

Figure 90. Basic Timing Diagram of the TAP Controller Signals

Table 27.

Parameter

Description

Minimum

Maximum

Unit

TIMING CHARACTERISTICS

tTCK

TCK period

tSTAP

TDI, TMS setup before TCK high

tHTAP

TDI, TMS hold after TCK high

tSSYS

System inputs setup before TCK high

tHSYS

System inputs hold after TCK high

tTRSTW

TRST pulse width (measured in TCK cycles)

TCK

SWITCHING CHARACTERISTICS

tDTDO

TDO delay from TCK low

tDSYS

System output delay after TCK low

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