AD9148BPCZ datasheet(57/73 Pages) AD

57 / 73 page

Preliminary Technical Data

AD9148

Rev. PrA | Page 57 of 73

CLK_P/CLK_N

(PIN B6 AND PIN A6)

ADC

VCO

LOOP

FILTER

REFCLK_P/REFCLK_N

(PIN B9 AND PIN A9)

0x0E[3:0]

PLL CONTROL

VOLTAGE

0x0D[1:0]

0x0D[3:2]

0x0D[7:6]

÷N1

÷N0

0x06[7:6]

PLL LOCK

PLL LOCK LOST

PHASE

DETECTION

0x0A[7]

PLL ENABLE

DACCLK

PC_CLK

÷N2

Figure 72. PLL Clock Multiplication Circuit

CLOCK MULTIPLICATION

The on-chip PLL clock multiplier circuit can be used to generate

the DAC sample rate clock from a lower frequency reference clock.

When the PLL clock multiplier is enabled (Register 0x0A[7] = 1),

the clock multiplication circuit generates the DAC sample clock

from the lower rate REFCLK input. The functional diagram of

the clock multiplier is shown in Figure 72.

The clock multiplication circuit operates such that the VCO

outputs a frequency, fVCO, equal to the REFCLK input signal

frequency multiplied by N0 × N1.

fVCO = fREFCLK × (N0 × N1)

The DAC sample clock frequency, fDACCLK, is equal to

fDACCLK = fREFCLK × N1

The output frequency of the VCO must be chosen to keep fVCO in

the optimal operating range of 1.0 GHz to 2.1 GHz. The frequency

of the reference clock and the values of N1 and N0 must be chosen

so that the desired DACCLK frequency can be synthesized and

the VCO output frequency is in the correct range.

PLL Bias Settings

There are four bias settings for the PLL circuitry that should be

programmed to their nominal values. The PLL values shown in

Table 24 are the recommended settings for these parameters.

Configuring the VCO Tuning Band

The PLL VCO has a valid operating range from approximately

1.0 GHz to 2.1 GHz covered in 63 overlapping frequency bands.

For any desired VCO output frequency, there may be several

valid PLL band select values. The frequency bands of a typical

device are shown in Figure 73. Device-to-device variations and

operating temperature affect the actual band frequency range.

Therefore, it is required that the optimal PLL band select value

be determined for each individual device.

1000

2200

2000

1800

1600

1400

1200

VCO FREQUENCY (MHz)

Figure 73. PLL Lock Range Overtemperature for a Typical Device

Table 24. PLL Settings

Address

PLL SPI Control

Bit

Optimal Setting

PLL Loop Bandwidth

0x0C

[7:5]

110

PLL Control 1 Register[4:0]

0x0C

[4:0]

01001

PLL Cross Control Enable

0x0D

[4]

PLL Ctrl (Test) Register[7:0]

0x79

[7:0]

11111111

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