AD9148BPCZ datasheet(6/73 Pages) AD

6 / 73 page

AD9148

Preliminary Technical Data

Rev. PrA | Page 6 of 73

DIGITAL INPUT DATA TIMING SPECIFICATIONS

Table 3.

Parameter

Min

Typ

Max

Unit

LATENCY (DACCLK CYCLES)

1× Interpolation (With or Without Coarse Modulation)

Cycles

2× Interpolation (With or Without Coarse Modulation)

125

Cycles

4× Interpolation (With or Without Coarse Modulation)

254

Cycles

8× Interpolation (With or Without Coarse Modulation)

508

Cycles

Inverse Sinc (1× Interpolation)

Cycles

Inverse Sinc (2× Interpolation)

Cycles

Inverse Sinc (4× Interpolation)

Cycles

Inverse Sinc (8× Interpolation)

Cycles

Fine Modulation

Cycles

Power–Up Time

TBD

Table 4. Maximum Rate

Maximum Rate (MSPS)

Interface Mode

fINTERFACE

fDATA

fHB1

fHB2

fHB3

fDAC

Dual Port Mode

620

310

620

1000

Single Port Mode or Byte Mode

1200

300

600

1000

FIFO A

FIFO B

2×

CLK GENERATOR

AND DISTRIBUTOR

fINTERFACE

fDATA

fHB1

fHB2

fHB3

fDAC

DAC1

AND

DAC2

DAC3

AND

DAC4

DCIA

DACCLK

DATA

PORT A

DATA

PORT B

DATA

ASSEMBLER

INPUT

LATCH

DCIB

DATA

ASSEMBLER

INPUT

LATCH

WRITE PTR A

WRITE PTR B

INTERFACE

MODE

ONE DCI

DATAPATH

2×

Figure 3. Defining Maximum Rates

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