AD9148BPCZ datasheet(41/73 Pages) AD

41 / 73 page

Preliminary Technical Data

AD9148

Rev. PrA | Page 41 of 73

FIFO OPERATION

DAC1

AND

DAC2

32 BITS

÷INT

DCIA

DCIB

DACCLK

DATA

PORT A

DATA

PORT B

DATA

PATHS

DATA

ASSEMBLER

INPUT

LATCH

DATA

ASSEMBLER

INPUT

LATCH

REG 0

REG 1

REG 2

REG 3

REG 4

REG 5

REG 6

REG 7

REG 0

REG 1

REG 2

REG 3

REG 4

REG 5

REG 6

REG 7

DAC3

AND

DAC4

DATA

PATHS

WRITE PTR

RESET

WRITE PTR

RESET

READ

PTR

RESET

SYNC

LOGIC

FIFO RATE/

DATA RATE

32 BITS

FRAME B

FRAME A

LOGIC

INTERFACE

MODE

ONE

DCI

WRITE PTR B

WRITE PTR A

Figure 49. Block Diagram of FIFO

The AD9148 contains two 32-bit wide, 8-word deep FIFOs (one

per dual DAC) designed to relax the timing relationship between

the data arriving at the DAC input ports and the internal DAC

data rate clock. The FIFOs can also be used to provide an adjustable

pipeline delay between the DCIx clocks and the DACCLK

allowing re-alignment of data input in a multichip system. This

significantly increases the timing budget of the interface.

Figure 49 shows the block diagram of the data path through the

FIFO. The data is latched into the device, is formatted, and is

then written into the FIFO register determined by the FIFO

write pointer. The value of the write pointer is incremented

every time a new word is loaded into the FIFO. Meanwhile, data

is read from the FIFO register determined by the read pointer

and fed into the digital data path. The value of the read pointer

is updated every time data is read into the data path from the

FIFO. This happens at the data rate that is the DACCLK rate

divided by the interpolation ratio. The difference between the

write and read pointers represent the FIFO pipeline delay and

are important to take into account when understanding the

overall pipeline delay of the AD9148.

In single port and byte interface modes, the incoming digital

data is sampled at twice the data rate (DCIA). The data is then

assembled based on the interface mode. At the output of the

data assembler block, the data samples for DAC 1 and DAC 2 are

written to FIFO A and the data samples for DAC 3 and DAC 4 are

written to FIFO B at the data rate.

Valid data is transmitted through the FIFO as long as the FIFO

does not overflow or become empty. An overflow or empty

condition of the FIFO is the same as the write pointer and the

read pointer being equal. When both pointers are equal, an attempt

is made to read and write a single FIFO register simultaneously.

This simultaneous register access leads to unreliable data transfer

through the FIFO and must be avoided.

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