AD9148BPCZ datasheet(44/73 Pages) AD

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AD9148

Preliminary Technical Data

Rev. PrA | Page 44 of 73

DEVICE SYNCHRONIZATION

SYNCHRONIZING MULTIPLE DEVICES

System demands may require that the outputs of multiple DACs

be synchronized with each other or with a system clock. Systems

that support transmit diversity or beam-forming, where multiple

antennas are used to transmit a correlated signal, require multiple

DAC outputs to be phase aligned with each other. Systems with

a time-division multiplexing transmit chain may require one or

more DACs to be synchronized with a system-level reference clock.

Multiple devices are considered synchronized to each other

when the state of the clock generation state machines is identical

for all parts and time aligned data is being read from the FIFOs

of all parts simultaneously. Devices are considered synchronized to

a system clock when there is a fixed and known relationship

between the clock generation state machine and the data being

read from the FIFO and a particular clock edge of the system

clock. The AD9148 has provisions for enabling multiple devices to

be synchronized to each other or to a system clock.

The AD9148 supports synchronization in two different modes,

data rate mode and FIFO rate mode. The two modes are

distinguished by the lowest rate clock that the synchronization

logic attempts to synchronize. In data rate mode, the input data

rate represents the lowest synchronized clock. In FIFO rate mode,

the FIFO rate, which is the data rate divided by the FIFO depth

of 8, represents the lowest rate clock. The advantage of the FIFO

rate synchronization is increased setup and hold times of DCI

relative to the CLK input. When in data rate synchronization

mode, the elasticity of the FIFO is not used to absorb timing

variations between the data source and DAC, resulting in

tighter setup and hold time requirements.

The method chosen for providing the DAC sampling clock directly

impacts the synchronization methods available. When the device

clock multiplier is used, only data rate synchronization is

available. When the DAC sampling clock is sourced directly,

both data rate mode and FIFO rate mode synchronization are

available.

SYNCHRONIZATION WITH CLOCK MULTIPLICATION

When using the clock multiplier to generate the DACCLK, the

REFCLK/SYNC input signal acts as both the reference clock for

the PLL-based clock multiplier and as the synchronization

signal. To synchronize devices, the REFCLK/ SYNC signal must

be distributed with low skew to all of the devices to be

synchronized. Skew between the REFCLK/SYNC signals of

different devices show up directly as a timing mismatch at the

DAC outputs.

The frequency of the REFCLK/SYNC signal is typically equal to

the input data rate. The FRAME signal and DCI signals can be

created in the FPGA along with the data. A circuit diagram of a

typical configuration is shown in Figure 52.

SYSTEM CLOCK

FPGA

LOW SKEW

CLOCK DRIVER

MATCHED

LENGTH TRACES

MATCHED

LENGTH TRACES

REFCLK/SYNC

FRAME

DCI

REFCLK/SYNC

FRAME

DCI

OUT1

OUT2

Figure 52. Typical Circuit Diagram for Synchronizing Devices with Clock Multiplication Enabled

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