AD9148BPCZ datasheet(47/73 Pages) AD

47 / 73 page

Preliminary Technical Data

AD9148

Rev. PrA | Page 47 of 73

Figure 55 shows the synchronization signal timing with 2×

interpolation, so that fDCI = ½ × fCLK. The SYNC input is shown

equal to the DCI rate. The maximum frequency at which the device

can be resynchronized in data rate mode can be expressed as

DATA

SYNC

for any positive integer, N.

Generally, for values of N equal to or greater than 3, the FIFO

rate synchronization mode is chosen.

FIFO Rate Mode Synchronization

The following procedure outlines the steps required to synchronize

multiple devices in FIFO rate mode. The procedure assumes

that the CLK and REFCLK/SYNC signals are applied to all of the

devices. Each individual device must follow the procedure.

The procedure for FIFO rate synchronization when directly

sourcing the DAC sampling clock follows:

Configure for FIFO rate, periodic synchronization by writing

0x80 to the sync control register (Register 0x10). Additional

synchronization options are available and are described in

the Additional Synchronization Features section.

Poll the sync locked bit (Bit 6, Register 0x12) to verify that

the device is back-end synchronized. A high level on this

bit indicates that the clocks are running with a constant

and known phase relative to the sync signal.

Reset the FIFO by strobing the FRAME signal high for at

least the time interval needed to load complete data to the

four DACs. Resetting the FIFO ensures that the correct

data is being read from the FIFO of each of the devices

simultaneously. This completes the synchronization

procedure, and at this stage, all devices should be

synchronized.

To ensure that each of the DACs are updated with the correct

data on the same DACCLK edge, two timing relationships must

be met on each DAC. DCI (and data) must meet the setup and

hold times with respect to the rising edge of CLK, and REFCLK/

SYNC must also meet the setup and hold time with respect to

the rising edge of CLK. When resetting the FIFO, the FRAME

signal must be held high for at least the time interval needed to

load complete data to the four DACs (one DCI period for dual-

port mode, and two DCI periods for single-port or byte mode).

When these conditions are met, the outputs of the DACs will be

updated within tSKEW + tOUTDLY nanoseconds of each other. A

timing diagram that illustrates the timing requirements of the

input signals is shown in Figure 56.

CLK(1)

CLK(2)

SYNC(2)

FRAME(2)

DCI(2)

tSKEW

tH_SYNC

tSU_SYNC

Figure 56. Synchronization Signal Timing Requirements in FIFO Rate Mode,

2× Interpolation

Figure 56 shows the synchronization signal timing with 2×

interpolation, so that fDCI = ½ × fCLK. The SYNC input is shown

equal to the FIFO rate. The maximum frequency at which the

device can be resynchronized in FIFO rate mode can be expressed as

DATA

SYNC

8 ×

for any positive integer, N.

ADDITIONAL SYNCHRONIZATION FEATURES

The synchronization logic incorporates additional features that

provide means for querying the status of the synchronization

and for improving the robustness of the synchronization. For

more information on these features, see the Sync Status Bits

section and the Timing Optimization section.

Sync Status Bits

When the sync locked bit (Bit 6, Register 0x12) is set, it indicates

that the synchronization logic has reached alignment. This is

determined when the clock generation state machine phase is

constant. This takes between (11 + Averaging) × 64 and (11 +

Averaging) × 128 DACCLK cycles. This bit may optionally trigger

an IRQ, as described in the Interrupt Request Operation section.

When the sync lost bit (Bit 7, Register 0x12) is set, it indicates a

previously synchronized device has lost alignment. This bit is

latched and remains set until cleared by overwriting the register.

This bit may optionally trigger an IRQ as described in the

Interrupt Request Operation section.

The sync phase readback bits (Bits [7:0], Register 0x13) report

the current clock phase in 6.2 format. Bits[7:2] report which of

the 64 states (0 to 63) the clock is currently in. When averaging

is enabled, Bits[1:0] provide ¼ state accuracy (for 0, ¼, ½, and

¾). The lower two bits give an indication of timing margin

issues that may exist. If the sync sampling is error free, the

fractional clock state should be 00.

AD9148BPCZ bảng dữ liệu(PDF) 47 Page - Analog Devices

AD9148BPCZ bảng dữ liệu(HTML) 47 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

bảng dữ liệu tải về

Link URL