H5GQ1H24AFR-R0C datasheet(49/173 Pages) HYNIX

tên linh kiện	H5GQ1H24AFR-R0C

Giải thích chi tiết về linh kiện	1Gb (32Mx32) GDDR5 SGRAM

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

will be increased. With positive offset steps the drive strengths will be increased and Ron will be

decreased. With negative offset steps the termin‐ation value will be increased. With positive offset steps

the termination value will be decreased.

IV curves and AC timings are only guaranteed with zero offset.

Figure 26. Impedance Offsets

Calibration

Engine

120

Ohms

VSSQ

Pullup

Impedance

Pulldown

Impedance

Offset

PU Driver

Offset

PD Driver

ADD/CMD

Termination

Impedance

Offset

ADD/CMD Termination

DQ/DBI#/WCK

Termination

Impedance

Offset

DQ/DBI#/WCK Termination

Autocalibrated

Impedance

Note: sum of offset + auto‐

calibrated impedance cannot

exceed maximum / minimum

available impedance steps

Fixed Impedance

nominal (60/40)

Auto/Fixed

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