H5GQ1H24AFR-R0C datasheet(37/173 Pages) HYNIX

tên linh kiện	H5GQ1H24AFR-R0C

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

Data from any RDTR burst may be concatenated with data from a subsequent RDTR command. A contin‐

uous flow of data can be maintained. The first data element from the new burst follows the last element of

a completed burst. The new RDTR command should be issued after the first RDTR command according to

the tCCDS timing.

A WRTR can be issued any time after a RDTR command as long as the bus turn around time tRTW is met.

The total number of RDTR commands modulo FIFO depth must be equal to total number of WRTR com‐

mands modulo FIFO depth when used in conjunction with WRTR. No READ or WRITE commands are

allowed between WRTR and RDTR.

The total number of RDTR commands modulo FIFO depth must be equal to the total number of LDFF

commands to burst position 7 modulo FIFO depth when used in conjunction with LDFF. No READ or

WRITE commands are allowed between LDFF and RDTR.

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