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H5GQ1H24AFR-R0C bảng dữ liệu(PDF) 89 Page - Hynix Semiconductor |
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H5GQ1H24AFR-R0C bảng dữ liệu(HTML) 89 Page - Hynix Semiconductor |
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89 / 173 page ![]() This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 89 H5GQ1H24AFR Figure 56. Single READ without EDC 3. Before the READ command, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met. 4. tWCK2DQO = 0 is shown for illustration purposes. DBI CL = CLmrs = 6 Bank a, Col n Col n CK CK# DQ DBI# T0 T1 T2 T5 T6n T6 T7n T8 T9 T10 T7 WCK# DONʹT CARE TRANSITIONING DATA DO DO DBI n+7 n+7 n n ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ODT Disabled ODT Enabled ODT Enabled ODT ( ) ( ) ( ) ( ) 1. CLmrs = 6 is shown as an example. Actual supported values will be found in the MR and AC timings sections. 2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK. Notes: EDC Hold Pattern EDC WCK ADDRESS NOP READ NOP NOP NOP NOP NOP NOP NOP COMMAND ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) |
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