H5GQ1H24AFR-R0C datasheet(33/173 Pages) HYNIX

33 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

Figure 16: Data Paths used for Read and Write Training

LDFF Command

The LDFF command (Figure 17) is used to securely load data to the GDDR5 SGRAM Read FIFOs via the

address bus. Depending on the GDDR5 SGRAM READ FIFO depth nFIFO 6, any bit pattern of length 32‐

48 can be loaded uniquely to every DQ, DBI# and EDC pin within a byte. The FIFO depth is fixed by

design and can be read via the Vendor ID function.

Eight LDFF commands are required to fill one FIFO stage; each LDFF command loads one burst position,

and the bank addresses BA0‐BA2 select the burst position from 0 to 7.

The data pattern is conveyed on address pins A0‐A7 for DQ0‐DQ7, A9 for DBI0#, and BA3 for EDC0; the

data are internally replicated to all 4 bytes, as shown in Figure 18.

WRTR strobe

(CK domain)

WRTR

FIFO 6 × 72=432 bits per byte

RDTR strobe

(WCK)

Reverse

DBI

DRAM

Core

WRTR

output

pointer

input

pointer

DQ0‐DQ7

DBI0#

EDC0

e.g. 500Mbps

DBI

e.g. 4Gbps

e.g.

500Mbps

RDTR strobe

(WCK)

LDFF

ADDR

DEMUX

LDFF

BA0‐BA2

Notes:

1) FIFO depth of 5 shown; supported FIFO depths: 4, 5 or 6

2) data paths shown for 1 of 4 bytes (byte 0)

Address

Path

output

pointer

input

pointer

8:1

Parallel to Serial

Converter

Serial to Parallel

Converter

8:1

Parallel to Serial

Converter

CRC strobe

LDFF strobe (burst 7)

WRTR strobe

LDFF strobe (burst 7)

CRC8

Data path used with RDTR

Data path used with WRTR

CRC FIFO 6 × 8 =48 bits per byte

Data path used with LDFF

Data path used with LDFF/WRTR

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