ATmega16U4 datasheet(149/408 Pages) ATMEL

149 / 408 page

149

7766D–AVR–01/09

ATmega16U4/ATmega32U4

15.6.2

Enhanced Compare/PWM mode

When the bit ENHC4 of TCCR4E register is set, the Enhanced Compare/PWM mode is enabled.

This mode allows user to add an accuracy bit to Output Compare Register OCR4A, OCR4B and

OCR4D. Like explained previously, a compare condition appears when one of the three Output

Compare Registers (OCR4A/B/D) matches the value of TCNT4 (10-bits resolution). In basic

PWM Mode, the corresponding enabled output toggles on the Compare Match. The Enhanced

Compare/PWM mode introduces a bit that determines on which internal clock edge the Com-

pare Match condition is actually signalled. That means that the corresponding outputs will toggle

on the standard clock edge (like in Normal mode) if the LSB of OCR4A/B/D is ‘0’, or on the oppo-

site (next) edge if the LSB is ‘1’.

User will notice that between Normal and Enhanced PWM modes, the output frequency will be

identical, while the PWM resolution will be better in second case.

Writing to the Output Compare registers OCR4A/B/D or reading them will be identical in both

modes. In Enhanced mode, user must just consider that the TC4H register can be up to 3-bits

wide (and have the same behavior than during 2-bits operation). That will concern OCR4A,

OCR4B and OCR4D registers accesses only. Indeed, the OCR4C register must not include the

additional accuracy bit, and remains in the resolution that determines the output signal period.

Figure 15-10. How register access works in Enhanced mode

That figure shows that the true OCR4A/B/D value corresponds to the value loaded by the user

shifted on the right in order to transfer the least significant bit directly to the Waveform genera-

tion module.

The maximum available resolution is 11-bits, but any other resolution can be specified. For

example, a 8-bits resolution will allow to obtain the same frequency than a Normal PWM mode

with 7-bits resolution.

Example:

– PLL Postcaler output = 64 MHz, No Prescaler on Timer/Counter4.

– Setting OCR4C = 0x7F determines a full 7-bits theoretical resolution, and so a 500kHz

output frequency.

(TC4H)

(OCR4A/B/D)

Output Compare Module A/B/D

Waveform Generation

Enhanced

Mode

Pin Toggle

True

OCR4A/B/D

User Interface Side

Timer Logic Side

ENHC4

TCNT4<9:0>

OCR4C<9:0>

Configuration

bits

ATmega16U4 bảng dữ liệu(PDF) 149 Page - ATMEL Corporation

ATmega16U4 bảng dữ liệu(HTML) 149 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL