ATmega16U4 datasheet(40/408 Pages) ATMEL

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7766D–AVR–01/09

ATmega16U4/ATmega32U4

• Bit 1 – PLLE: PLL Enable

When the PLLE is set, the PLL is started. Note that the Calibrated 8 MHz Internal RC oscillator is

automatically enabled when the PLLE bit is set and with PINMUX (see PLLFRQ register) is set.

The PLL must be disabled before entering Power down mode in order to stop Internal RC Oscil-

lator and avoid extra-consumption.

• Bit 0 – PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock. After the PLL is enabled, it

takes about several ms for the PLL to lock. To clear PLOCK, clear PLLE.

6.9.3

PLL Frequency Control Register – PLLFRQ

• Bit 7– PINMUX: PLL Input Multiplexer

This bit selects the clock input of the PLL:

– PINMUX = 0: the PLL input is connected to the PLL Prescaler, that has the Primary

System Clock as source

– PINMUX = 1: the PLL input is directly connected to the Internal Calibrated 8MHz RC

Oscillator. This mode allows to work in USB Low Speed mode with no crystal or

using a crystal with a value different of 8/16MHz.

• Bit 6– PLLUSB: PLL Postcaler for USB Peripheral

This bit select the division factor between the PLL output frequency and the USB module input

frequency:

– PLLUSB = 0: no division, direct connection (if PLL Output = 48 MHz)

– PLLUSB = 1: PLL Output frequency is divided by 2 and sent to USB module (if PLL

Output = 96MHz)

• Bit 5..4 – PLLTM1:0: PLL Postcaler for High Speed Timer

These bits codes for the division factor between the PLL Output Frequency and the High Speed

Timer input frequency.

Note that the division factor 1.5 will introduce some jitter in the clock, but keeping the error null

since the average duty cycle is 50%. See Figure 6-5 for more details.

Bit

$32

PINMUX

PLLUSB

PLLTM1

PLLTM0

PDIV3

PDIV2

PDIV1

PDIV0

PLLFRQ

Read/Write

R/WR/W

Initial Value

PLLTM1

PLLTM0

PLL Postcaler Factor for High-Speed Timer

0 (Disconnected)

1.5

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