ATmega16U4 datasheet(26/408 Pages) ATMEL

26 / 408 page

7766D–AVR–01/09

ATmega16U4/ATmega32U4

5.4

I/O Memory

The I/O space definition of the ATmega16U4/ATmega32U4 is shown in “Register Summary” on

page 388.

All ATmega16U4/ATmega32U4 I/Os and peripherals are placed in the I/O space. All I/O loca-

tions may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data

between the 32 general purpose working registers and the I/O space. I/O Registers within the

address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In

these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

Refer to the instruction set section for more details. When using the I/O specific commands IN

and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data

space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega16U4/ATmega32U4 is a complex microcontroller with more peripheral units than can be

supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the

Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-

tions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

5.4.1

General Purpose I/O Registers

The ATmega16U4/ATmega32U4 contains three General Purpose I/O Registers. These registers

can be used for storing any information, and they are particularly useful for storing global vari-

ables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F

are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

5.4.2

General Purpose I/O Register 2 – GPIOR2

5.4.3

General Purpose I/O Register 1 – GPIOR1

5.4.4

General Purpose I/O Register 0 – GPIOR0

Bit

7654

MSB

LSB

GPIOR2

Read/Write

R/W

Initial Value

0000

Bit

7654

MSB

LSB

GPIOR1

Read/Write

R/W

Initial Value

0000

Bit

7654

MSB

LSB

GPIOR0

Read/Write

R/W

Initial Value

0000

ATmega16U4 bảng dữ liệu(PDF) 26 Page - ATMEL Corporation

ATmega16U4 bảng dữ liệu(HTML) 26 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL