ATmega16U4 datasheet(147/408 Pages) ATMEL

147 / 408 page

147

7766D–AVR–01/09

ATmega16U4/ATmega32U4

The length of the counting period is user adjustable by selecting the dead time prescaler setting

by using the DTPS41:40 control bits, and selecting then the dead time value in I/O register DT4.

The DT4 register consists of two 4-bit fields, DT4H and DT4L that control the dead time periods

of the PWM output and its' complementary output separately in terms of the number of pres-

caled dead time generator clock cycles. Thus the rising edge of OC4x and OC4x can have

different dead time periods as the t

non-overlap / rising edge is adjusted by the 4-bit DT4H value and the

non-overlap / falling edge is adjusted by the 4-bit DT4L value.

Figure 15-8. The Complementary Output Pair, COM4x1:0 = 1

15.6

Compare Match Output Unit

The Compare Output Mode (COM4x1:0) bits have two functions. The Waveform Generator uses

the COM4x1:0 bits for defining the inverted or non-inverted Waveform Output (OCW4x) at the

next Compare Match. Also, the COM4x1:0 bits control the OC4x and OC4x pin output source.

Figure 15-9 shows a simplified schematic of the logic affected by the COM4x1:0 bit setting. The

I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general

I/O Port Control Registers (DDR and PORT) that are affected by the COM4x1:0 bits are shown.

In Normal Mode (non-PWM) the Dead Time Generator is disabled and it is working like a syn-

chronizer: the Output Compare (OC4x) is delayed from the Waveform Output (OCW4x) by one

timer clock cycle. Whereas in Fast PWM Mode and in Phase and Frequency Correct PWM

Mode when the COM4x1:0 bits are set to “01” both the non-inverted and the inverted Output

Compare output are generated, and an user programmable Dead Time delay is inserted for

these complementary output pairs (OC4x and OC4x). The functionality in PWM modes is similar

to Normal mode when any other COM4x1:0 bit setup is used. When referring to the OC4x state,

the reference is for the Output Compare output (OC4x) from the Dead Time Generator, not the

OC4x pin. If a system reset occur, the OC4x is reset to “0”.

The general I/O port function is overridden by the Output Compare (OC4x / OC4x) from the

Dead Time Generator if either of the COM4x1:0 bits are set. However, the OC4x pin direction

(input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data

Direction Register bit for the OC4x and OC4x pins (DDR_OC4x and DDR_OC4x) must be set as

output before the OC4x and OC4x values are visible on the pin. The port override function is

independent of the Output Compare mode.

The design of the Output Compare Pin Configuration logic allows initialization of the OC4x state

before the output is enabled. Note that some COM4x1:0 bit settings are reserved for certain

modes of operation. For Output Compare Pin Configurations refer to Table 15-2 on page 152,

Table 15-3 on page 153, Table 15-4 on page 155, and Table 15-5 on page 156.

OCnx

(COMnx = 1)

t non-overlap / rising edge

t non-overlap / falling edge

OCnx

OCWnx

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