PIC18F44J10 datasheet(162/368 Pages) MICROCHIP

162 / 368 page

PIC18F45J10 FAMILY

DS39682E-page 160

SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE)

R/W-0

R-0

SMP

CKE

D/A

P(1)

S(1)

R/W

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

SMP:

Slew Rate Control bit

In Master or Slave mode:

= Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

= Slew rate control enabled for High-Speed mode (400 kHz)

bit 6

CKE:

SMBus Select bit

In Master or Slave mode:

= Enable SMBus specific inputs

= Disable SMBus specific inputs

bit 5

D/A:

Data/Address bit

In Master mode:

Reserved.

In Slave mode:

= Indicates that the last byte received or transmitted was data

= Indicates that the last byte received or transmitted was address

bit 4

Stop bit(1)

= Indicates that a Stop bit has been detected last

= Stop bit was not detected last

bit 3

Start bit(1)

= Indicates that a Start bit has been detected last

= Start bit was not detected last

bit 2

R/W:

Read/Write Information bit (I2C mode only)

In Slave mode:(2)

= Read

= Write

In Master mode:(3)

= Transmit is in progress

= Transmit is not in progress

bit 1

UA:

Update Address bit (10-Bit Slave mode only)

= Indicates that the user needs to update the address in the SSPxADD register

= Address does not need to be updated

bit 0

BF:

Buffer Full Status bit

In Transmit mode:

= SSPxBUF is full

= SSPxBUF is empty

In Receive mode:

= SSPxBUF is full (does not include the ACK and Stop bits)

= SSPxBUF is empty (does not include the ACK and Stop bits)

Note 1:

This bit is cleared on Reset and when SSPEN is cleared.

This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next Start bit, Stop bit or not ACK bit.

ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.

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