PIC18F44J10 datasheet(153/368 Pages) MICROCHIP

153 / 368 page

DS39682E-page 151

PIC18F45J10 FAMILY

SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE)

R/W-0

WCOL

SSPOV(1)

SSPEN(2)

CKP

SSPM3(3)

SSPM2(3)

SSPM1(3)

SSPM0(3)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

WCOL:

Write Collision Detect bit

= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in

software)

= No collision

bit 6

SSPOV:

Receive Overflow Indicator bit(1)

SPI Slave mode:

= A new byte is received while the SSPxBUF register is still holding the previous data. In case of

overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read

the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in

software).

= No overflow

bit 5

SSPEN:

Master Synchronous Serial Port Enable bit(2)

= Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins

= Disables serial port and configures these pins as I/O port pins

bit 4

CKP:

Clock Polarity Select bit

= Idle state for clock is a high level

= Idle state for clock is a low level

bit 3-0

SSPM<3:0>:

Master Synchronous Serial Port Mode Select bits(3)

0101

= SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin

0100

= SPI Slave mode, clock = SCKx pin, SSx pin control enabled

0011

= SPI Master mode, clock = TMR2 output/2

0010

= SPI Master mode, clock = FOSC/64

0001

= SPI Master mode, clock = FOSC/16

0000

= SPI Master mode, clock = FOSC/4

Note 1:

In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by

writing to the SSPxBUF register.

When enabled, these pins must be properly configured as input or output.

Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.

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