PIC18F44J10 datasheet(146/368 Pages) MICROCHIP

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PIC18F45J10 FAMILY

DS39682E-page 144

15.4.6

PROGRAMMABLE DEAD-BAND

DELAY

In half-bridge applications, where all power switches

are modulated at the PWM frequency at all times, the

power switches normally require more time to turn off

than to turn on. If both the upper and lower power

switches are switched at the same time (one turned on

and the other turned off), both switches may be on for

a short period of time until one switch completely turns

off. During this brief interval, a very high current (shoot-

through current

) may flow through both power

switches, shorting the bridge supply. To avoid this

potentially destructive shoot-through current from

flowing during switching, turning on either of the power

switches is normally delayed to allow the other switch

to completely turn off.

In the Half-Bridge Output mode, a digitally programmable

dead-band delay is available to avoid shoot-through

current from destroying the bridge power switches. The

delay occurs at the signal transition from the nonactive

state to the active state. See Figure 15-4 for an

illustration. Bits PDC<6:0> of the ECCP1DEL register

(Register 15-2) set the delay period in terms of microcon-

troller instruction cycles (TCY or 4 TOSC). These bits are

not available in 28-pin devices as the standard CCP

module does not support half-bridge operation.

15.4.7

ENHANCED PWM AUTO-SHUTDOWN

When the ECCP1 is programmed for any of the

Enhanced PWM modes, the active output pins may be

configured for auto-shutdown. Auto-shutdown immedi-

ately places the Enhanced PWM output pins into a

defined shutdown state when a shutdown event occurs.

A shutdown event can be caused by either of the

comparator modules, a low level on the Fault input pin

(FLT0) or any combination of these three sources. The

comparators may be used to monitor a voltage input

proportional to a current being monitored in the bridge

circuit. If the voltage exceeds a threshold, the

comparator switches state and triggers a shutdown.

Alternatively, a low digital signal on FLT0 can also trigger

a shutdown. The auto-shutdown feature can be disabled

by not selecting any auto-shutdown sources. The auto-

shutdown sources to be used are selected using the

ECCPAS<2:0> bits (bits<6:4> of the ECCP1AS

When a shutdown occurs, the output pins are

asynchronously placed in their shutdown states,

specified by the PSSAC<1:0> and PSSBD<1:0> bits

(ECCPAS<3:0>). Each pin pair (P1A/P1C and P1B/

P1D) may be set to drive high, drive low or be tri-stated

(not driving). The ECCPASE bit (ECCP1AS<7>) is also

set to hold the Enhanced PWM outputs in their

shutdown states.

The ECCPASE bit is set by hardware when a shutdown

event occurs. If automatic restarts are not enabled, the

ECCPASE bit is cleared by firmware when the cause of

the shutdown clears. If automatic restarts are enabled,

the ECCPASE bit is automatically cleared when the

cause of the auto-shutdown has cleared.

If the ECCPASE bit is set when a PWM period begins,

the PWM outputs remain in their shutdown state for that

entire PWM period. When the ECCPASE bit is cleared,

the PWM outputs will return to normal operation at the

beginning of the next PWM period.

Note:

Programmable dead-band delay is not

implemented in 28-pin devices with

standard CCP modules.

Note:

Writing to the ECCPASE bit is disabled

while a shutdown condition is active.

ECCP1DEL: PWM DEAD-BAND DELAY REGISTER

R/W-0

PRSEN

PDC6(1)

PDC5(1)

PDC4(1)

PDC3(1)

PDC2(1)

PDC1(1)

PDC0(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

PRSEN:

PWM Restart Enable bit

= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away;

the PWM restarts automatically

= Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM

bit 6-0

PDC<6:0>:

PWM Delay Count bits(1)

Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM

signal to transition to active.

Note 1:

Reserved on 28-pin devices; maintain these bits clear.

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