PIC18F44J10 datasheet(123/368 Pages) MICROCHIP

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DS39682E-page 121

PIC18F45J10 FAMILY

FIGURE 12-2:

TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

12.2

Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes

(see Figure 12-2). When the RD16 control bit

(T1CON<7>) is set, the address for TMR1H is mapped

to a buffer register for the high byte of Timer1. A read

from TMR1L will load the contents of the high byte of

Timer1 into the Timer1 High Byte Buffer register. This

provides the user with the ability to accurately read all

16 bits of Timer1 without having to determine whether a

read of the high byte, followed by a read of the low byte,

has become invalid due to a rollover between reads.

A write to the high byte of Timer1 must also take place

through the TMR1H Buffer register. The Timer1 high

byte is updated with the contents of TMR1H when a

write occurs to TMR1L. This allows a user to write all

16 bits to both the high and low bytes of Timer1 at once.

The high byte of Timer1 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer1 High Byte Buffer register.

Writes to TMR1H do not clear the Timer1 prescaler.

The prescaler is only cleared on writes to TMR1L.

12.3

Timer1 Oscillator

An on-chip crystal oscillator circuit is incorporated

between pins T1OSI (input) and T1OSO (amplifier

output). It is enabled by setting the Timer1 Oscillator

Enable bit, T1OSCEN (T1CON<3>). The oscillator is a

low-power circuit rated for 32 kHz crystals. It will continue

to run during all power-managed modes. The circuit for a

typical oscillator is shown in Figure 12-3. Table 12-1

shows the capacitor selection for the Timer1 oscillator.

The user must provide a software time delay to ensure

proper start-up of the Timer1 oscillator.

FIGURE 12-3:

EXTERNAL

COMPONENTS FOR THE

TIMER1 OSCILLATOR

T1SYNC

TMR1CS

T1CKPS<1:0>

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8

Synchronize

Detect

T1OSO/T1CKI

T1OSI

Note 1:

When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

TMR1L

Internal Data Bus

Set

TMR1IF

on Overflow

TMR1

TMR1H

High Byte

Read TMR1L

Write TMR1L

TMR1ON

Clear TMR1

(CCP Special Event Trigger)

Timer1 Oscillator

On/Off

Timer1

Timer1 Clock Input

Note:

See the Notes with Table 12-1 for additional

information about capacitor selection.

XTAL

PIC18F45J10

T1OSI

T1OSO

32.768 kHz

27 pF

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