PIC18F44J10 datasheet(116/368 Pages) MICROCHIP

116 / 368 page

PIC18F45J10 FAMILY

DS39682E-page 114

FIGURE 10-4:

PARALLEL SLAVE PORT WRITE WAVEFORMS

FIGURE 10-5:

PARALLEL SLAVE PORT READ WAVEFORMS

TABLE 10-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

PORTD(1)

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

LATD(1)

PORTD Data Latch Register (Read and Write to Data Latch)

TRISD(1)

PORTD Data Direction Control Register

PORTE(1)

—

RE2

RE1

RE0

LATE(1)

—

PORTE Data Latch Register

(Read and Write to Data Latch)

TRISE(1)

IBF

OBF

IBOV

PSPMODE

—

TRISE2

TRISE1

TRISE0

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSP1IF

CCP1IF

TMR2IF

TMR1IF

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSP1IE

CCP1IE

TMR2IE

TMR1IE

IPR1

PSPIP(1)

ADIP

RCIP

TXIP

SSP1IP

CCP1IP

TMR2IP

TMR1IP

ADCON1

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

Legend:

— = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.

Note 1:

These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.

IBF

OBF

PSPIF

PORTD<7:0>

IBF

PSPIF

OBF

PORTD<7:0>

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