TCM4400EPET datasheet(20/64 Pages) TI

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TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

uplink timing considerations

Figure 1 shows the timing diagram for the uplink operation.

Timing for power up, offset calibration, data transmission, and power ramp-up are driven by control bits applied

to BULON (base uplink on), BCAL (calibration) and BENA (enable). The burst content including guard bits, tail

bits, and data bits is sent by the DSP by way of the DSP interface and then stored by the TCM4400E in a burst

buffer. Transmission start is indicated by the control bit BENA when the BULON is active. The transmission,

sequencing, and power ramp-up are then controlled by an on-chip burst sequencer with a one-quarter-bit timing

accuracy. For a detailed description of the baseband in length path, see the functional description of the

baseband uplink path in the

Principles of Operation section.

tsu2

tw1

tsu3

th2

tsu1

tr1

th1

tf1

th3

BULON

BCAL

BENA

MODULATION

APC

tw2

Figure 1. Uplink Timing Diagram

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