TCM4400EPET datasheet(42/64 Pages) TI

42 / 64 page

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

serial interface (continued)

Table 2. Microcontroller Clocking Schemes

UPOL

UPHA

MCU CLOCKING SCHEME

Falling edge without delay

Falling edge with delay

Rising edge without delay

Rising edge with delay

DSP/MCU serial interface

The DSP/MCU serial interface not only configures the GSM baseboard and voice A/D and D/A conversion but

also transmits data to the DSP during downlink burst reactions. The following paragraphs describe the operation

of the serial interface in more detail.

DSP serial digital interface

The DSP serial digital interface (Figure 16) is used to transfer the baseband transmit and receive data, and it

is also used to access all internal programming registers of the device (baseband codec, voice codec, and

auxiliary RF functions). The format for the serial interface is 16 bits.

The baseband serial digital interface is a bidirectional (transmit/receive) serial port. Both receive and transmit

operations are double buffered and permit a continuous communication stream (16-bit data packets). The serial

port is fully static and functions with any arbitrary, low-clocking frequency.

Six terminals are used for the serial port interface (see Figure 4 for timing diagram). BCLKR is an I/O port for

the serial clock used to control the reception of the data BDR. At reset BCLKR is configured as an output and

the clock frequency is set to MCLK/3 (4.333 MHz with MCLK = 13 MHz); the clock signal is running permanently.

The port BCLKR can be reconfigured as an input by programming an internal register. In this case BCLKR is

provided by the DSP. It can run in burst mode to reduce power consumption. The receive frame synchronization

(BFSR) is used to identify the beginning of a data packet transfer on port BDR.

The transmitted serial data (BDX) is the serial data input; the transmit frame synchronization (BFSX) is used

to initiate the transmission of data. The transmit clock (BCLKX) is provided by the GSM baseband and voice

A/D and D/A converters with a MCLK frequency. The clock signal BCLKX can run in burst mode or continuous

mode, depending on the BCLKMODE bit. The downlink data bus (BFSX, BCLKX, BDX) can be driven to VSS

or placed in a high-impedance state when no data is to be transferred to the DSP. The BCLKDIR bit of the

BCTLREG register controls the direction of the BCLKR clock.

As with the voice serial interface, on extra clock cycle must be generated because the last 16-bit word received

on the DSP serial interface is latched on the next two falling BCLKR edges following the LSB. As for the voice

serial interface, one extra clock period is generated on the BCLKX before the first synchronization BFSX of the

downlink data sequence.

TCM4400EPET bảng dữ liệu(PDF) 42 Page - Texas Instruments

TCM4400EPET bảng dữ liệu(HTML) 42 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

bảng dữ liệu tải về

Link URL