TCM4400EPET datasheet(43/64 Pages) TI

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TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

DRR

RSR

DXR

XSR

Control

Logic

Control

Logic

Byte/Word

Counter

Byte/Word

Counter

Data Bus

Load

Clear

Clock

Clear

Clock

BDR

BFSR BCLKR BCLKX BFSX

BDX

Figure 16. DSP Serial Digital Interface

timing interface

The timing interface performs accurate timing control of baseband uplink and downlink paths. The timing

interface is a parallel asynchronous port with four control signals, refer to Figure 17. The BDLON bit controls

power on the downlink path of the baseband codec; the BULON bit controls power on the uplink path of the

baseband codec, and the BCAL bit controls the calibration of the active parts of the baseband codec selected

by BULON or BDLON.

The BENA bit controls the transmission of the reception of burst depending on which part of the baseband codec

is selected by the signals BULON or BDLON. These asynchronous inputs are internally synchronized with the

uplink and downlink internal clocks and stored in timing register TR. The timing register, TR, is a 6-bit register

containing the bits defined in Table 3.

Table 3. 6-Bit TR Register

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

ULON

ULCAL

ULSEND

DLON

DLCAL

DLREC

TR bit signification

ULON:

If set to 1, this bit turns on the uplink path of the baseband codec; if cleared to 0, the uplink path

is in power-down mode.

ULCAL:

When this bit is set to 1, the uplink offset autocalibration is active.

ULSEND:

A transition from 0 to 1 of ULSEND initiates the emission of a burst. The burst information

data, burst length, and power level need to be loaded in the corresponding registers using the

serial interface.

DLON:

If set at 1, this bit turns on the downlink path of the baseband codec; if cleared to 0, the

downlink path is in power-down mode.

DLCAL:

When this bit is set at 1, the downlink offset autocalibration is active.

DLREC:

A transition from 0 to 1 of DLREC initiates the transmission of data from the baseband codec

to the DSP using the serial interface.

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