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EP910 bảng dữ liệu(PDF) 30 Page - Altera Corporation

tên linh kiện EP910
Giải thích chi tiết về linh kiện  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
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nhà sản xuất  ALTERA [Altera Corporation]
Trang chủ  http://www.altera.com
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EP910 bảng dữ liệu(HTML) 30 Page - Altera Corporation

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Altera Corporation
Classic EPLD Family Data Sheet
Tables 21 and 22 show the timing parameters for EP910I devices.
Table 21. EP910I External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions EP910I-12 EP910I-15 EP910I-25 Non-Turbo
Adder
Unit
Min Max Min Max Min Max
(3)
tPD1
Input to non-registered output
C1 = 35 pF
12.0
15.0
25.0
40.0
ns
tPD2
I/O input to non-registered output
C1 = 35 pF
12.0
15.0
25.0
40.0
ns
tPZX
Input to output enable
C1 = 35 pF
15.0
18.0
28.0
40.0
ns
tPXZ
Input to output disable
C1 = 35 pF
(4)
15.0
18.0
28.0
40.0
ns
tCLR
Asynchronous output clear time
C1 = 35 pF
15.0
18.0
28.0
40.0
ns
fMAX
Global clock maximum frequency
(5)
125.0
100.0
62.5
0.0
MHz
tSU
Global clock input setup time
8.0
11.0
16.0
40.0
ns
tH
Global clock input hold time
0.0
0.0
0.0
0.0
ns
tCH
Global clock high time
5.0
6.0
10.0
0.0
ns
tCL
Global clock low time
5.0
6.0
10.0
0.0
ns
tCO1
Global clock to output delay
8.0
9.0
14.0
0.0
ns
tCNT
Global clock minimum clock period
C1 = 35 pF
13.0
15.0
25.0
40.0
ns
fCNT
Maximum internal global clock
frequency
(6)
76.9
66.6
40.0
0.0
MHz
tASU
Array clock input setup time
3.0
4.0
8.0
40.0
ns
tAH
Array clock input hold time
6.0
7.0
8.0
ns
tACH
Array clock high time
6.0
7.5
12.5
ns
tACL
Array clock low time
6.0
7.5
12.5
ns
tODH
Output data hold time after clock
C1 = 35 pF
(7)
1.0
1.0
1.0
ns
tACO1
Array clock to output delay
C1 = 35 pF
16.0
18.0
22.0
40.0
ns
tACNT
Array clock minimum clock period
13.0
15.0
25.0
40.0
ns
fACNT
Maximum internal array clock
frequency
(6)
76.9
66.6
40.0
MHz



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