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TDF8599TH bảng dữ liệu(PDF) 41 Page - NXP Semiconductors |
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TDF8599TH bảng dữ liệu(HTML) 41 Page - NXP Semiconductors |
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41 / 52 page ![]() TDF8599_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 41 of 52 NXP Semiconductors TDF8599 Class-D power amplifier with load diagnostics Dual BTL mode (stereo) in non-I2C-bus mode with DC offset protection enabled Spread spectrum mode disabled. (1) See Figure 4 on page 7 for a diagram of the connection for pins EN and SEL_MUTE. (2) See Section 8.3.2 on page 9 for detailed information. (3) See Section 8.5.5 on page 16 for detailed information on disabling DC offset protection. Fig 42. Example application diagram for dual BTL in I2C-bus mode 001aai811 22 Ω 39 k Ω 10 k Ω 10 k Ω ≤33 kΩ 10 Ω 10 Ω 22 Ω 100 µF 35 V 100 µF 35 V 100 nF 15 nF 470 nF 100 nF 15 nF 470 pF 470 pF 470 pF 470 pF CLC CIN1P 470 nF CIN1N 470 nF CIN2P 470 nF 470 nF 100 nF 47 µF CIN2N LLC LLC CLC 100 nF PGND1 PGND1 VP1 VP1 VP1 VP2 VPA TDF8599 bead bead Rads bead bead OUT1N OUT1P OUT1N VP GND OUT1P VSTAB1 GNDD/HW 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 BOOT1N BOOT1P VP1 PGND1 PGND1 PGND2 VDDD 1000 µF 35 V 4.7 µF 100 nF 220 nF VSTAB2 DCP OSCIO 220 nF 22 Ω 10 Ω 10 Ω 22 Ω 100 nF 15 nF 100 nF 15 nF 470 pF 470 pF 470 pF 470 pF CLC LLC LLC CLC 100 nF PGND2 PGND2 VP2 VP2 OUT2P OUT2N OUT2P OUT2N BOOT2P BOOT2N VP2 PGND2 IN2N AGND IN2P IN1P ACGND SVRR EN SEL_MUTE(1) IN1N IN2N 100 nF 100 nF (2) CACGND enable(1) IN2P IN1P IN1N SCL SSM OSCSET VDDA SDA VPA VPA VPA stereo mode setting connect with µP MASTER MODE I2C-bus address select ADS DIAG MOD CLIP (3) |
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