TDF8599TH datasheet(20/52 Pages) NXP

20 / 52 page

TDF8599_1

Product data sheet

Rev. 01 — 13 November 2008

20 of 52

NXP Semiconductors

TDF8599

Class-D power ampliﬁer with load diagnostics

Remark: DC load detection identiﬁes a short circuited speaker as a valid speaker load.

OCP detection, using byte DB1[D3] for channel 1 and byte DB2[D3] for channel 2,

performs diagnostics on shorted loads. However, the diagnostics are performed after the

DC load detection cycle has ﬁnished and once the ampliﬁer is in Operating mode.

The result of the DC load detection is stored in DB1[D4] and DB2[D4].

Remark: After DC load detection has been performed, the DC load valid bit DB1[D6] must

be set. The DC load data bits are only valid when bit DB1[D6] = 1. When DC load

detection is interrupted by a sudden large change in supply voltage (triggered by UVP or

OVP) or if the ampliﬁer hangs up, the DC load valid bit is reset to DB1[D6] = 0. The DC

load enable bit DB2[D2] must be reset after the DC load protection cycle to release any

ampliﬁer hang-up. Once the DC load detection cycle has ﬁnished, DC load detection can

be restarted by toggling the DC load detection enable bit IB2[D2]. However, this can only

be used if both ampliﬁer channels have not been enabled with bit IB1[D1] or bit IB2[D1].

See Section 8.6.2.2 “Recommended start-up sequence with DC load detection enabled”

for detailed information.

8.6.2.2

Recommended start-up sequence with DC load detection enabled

The ﬂow diagram (Figure 20) illustrates the TDF8599’s ability to perform a DC load

detection without starting the ampliﬁers. After a DC load detection cycle ﬁnishes without

setting the DC load valid bit DB1[D6], DC load detection is repeated (when bit IB2[D2] is

toggled).

To limit the maximum number of DC load detection cycle loops, a counter and limit have

been added. The loop exits after the predeﬁned number of cycles (COUNTMAX), if the

DC load detection cycle ﬁnishes with an invalid detection.

Depending on the application needs the invalid DC load detection cycle can be handled

as follows:

• the ampliﬁer can be started without DC load detection

• the DC load detection loop can be executed again

A valid DC load detection cycle does not affect the normal ampliﬁer start-up timing.

Table 12.

Interpretation of DC load detection bits

DC load bits DB1[D4] and DB2[D4]

OCP bits DB1[D3] and DB2[D3]

Meaning

speaker load

shorted load

open load

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