M16CSLASH62 datasheet(158/615 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register

1-139

An attempt to read Port P71 (SCL) results in getting the terminal’s level regardless of the content of the

port direction register. The initial value of SDA transmission output in this mode goes to the value set in

port P70. The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and

of UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-

detection interrupt, and acknowledgment detection interrupt respectively.

The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA

terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection interrupt

refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL

terminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the

start condition detection, and set to “0” by the stop condition detection.

The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal

level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment

detection interrupt refers to the interrupt that occurs when SDA terminal’s level is detected already went

to “L” at the 9th transmission clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA1 request factor

select bits provides the means to start up the DMA transfer by the effect of acknowledgment detection.

Bit 1 of the UART2 special mode register (037716) is used as the arbitration lost detecting flag control bit.

Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal

data at the timing of the SCL rising edge. This detecting flag is located at bit 11 of the UART2 reception

buffer register (037F16, 037E16), and “1” is set in this flag when nonconformity is detected. Use the

arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by

byte. When setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the

arbitration lost detecting flag is set to “1” at the falling edge of the 9th transmission clock.

If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after complet-

ing the first byte acknowledge detect and before starting the next one byte transmission.

Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting

this bit to “1” goes the P71 data register to “0” in synchronization with the SCL terminal level going to “L”.

Figure 1.16.27 shows the functional block diagram for I2C mode. Setting “1” in the I2C mode select bit

(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock input-

output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output,

so the SDA output changes after SCL fully goes to “L”. The SDA digital delay select bit (bit 7 at address

037716) can be used to select between analog delay and digital delay. When digital delay is selected, the

amount of delay can be selected in the range of 2 cycles to 8 cycles of f1 using UART2 special mode

Table 1.16.10. Delay circuit select conditions

Digital delay is

selected

001

111

000

(000)

Analog delay is

selected

No delay

(000)

IICM

SDDS

Contents

When digital delay is selected, no analog delay is added. Only

digital delay is effective.

When DL is set to “000”, analog delay is selected no matter what

value is set in SDDS.

When SDDS is set to “0”, DL is initialized, so that DL =“000”.

When IICM = “0”, no delay circuit is selected. When IICM = “0”,

however, always make sure SDDS = “0”.

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