M16CSLASH62 datasheet(53/615 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Bus Control

1-34

(9) Software wait

A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address

000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).

A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the

wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.

When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been

reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two or three BCLK

cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring

to the recommended operating conditions (main clock input oscillation frequency) of the electric character-

________

istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register’s

bits 4 to 7 must be set to “0”.

When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for

each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register

_______

correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in

one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits

default to “0” after the microcomputer has been reset.

The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,

insert a software wait if using the multiplex bus to access the external memory area.

Table 1.9.8 shows the software wait and bus cycles. Figure 1.9.6 shows example of bus timing when

using software waits.

Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect

Area

Bus status

Wait bit

Bits 4 to 7 of chip select

control register

Bus cycle

Invalid

2 BCLK cycles

External

memory

area

Separate bus

1 BCLK cycle

Separate bus

2 BCLK cycles

Separate bus

0 (Note)

2 BCLK cycles

Multiplex bus

3 BCLK cycles

Multiplex bus

3 BCLK cycles

0 (Note)

SFR

Internal

ROM/RAM

Invalid

1 BCLK cycle

Invalid

2 BCLK cycles

Note: When using the RDY signal, always set to “0”.

Table 1.9.8. Software waits and bus cycles

(8) BCLK output

The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note).

When set to “1”, the output floating.

Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect

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