M16CSLASH62 datasheet(75/615 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupt

1-56

Interrupt sources without priority levels

Value set in the IPL

_______

Watchdog timer, NMI

Other

Not changed

Variation of IPL when Interrupt Request is Accepted

If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.

If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown

in Table 1.11.6 is set in the IPL.

Table 1.11.6. Relationship between interrupts without interrupt priority levels and IPL

Stack pointer (SP) value

Interrupt vector address

16-Bit bus, without wait

8-Bit bus, without wait

Even

Odd (Note 2)

Even

Odd

Even

Odd

18 cycles (Note 1)

19 cycles (Note 1)

20 cycles (Note 1)

Table 1.11.5. Time required for executing the interrupt sequence

Reset

Indeterminate

The indeterminate segment is dependent on the queue buffer.

If the queue buffer is ready to take an instruction, a read cycle occurs.

Indeterminate

SP-2

contents

SP-4

contents

vec

contents

vec+2

contents

Interrupt

information

Address

0000

Indeterminate

SP-2

SP-4

vec

vec+2

BCLK

Address bus

Data bus

Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the

DIVX instruction (without wait).

Time (b) is as shown in Table 1.11.5.

________

Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match

interrupt or of a single-step interrupt.

Note 2: Locate an interrupt vector address in an even address, if possible.

Figure 1.11.5. Time required for executing the interrupt sequence

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