M16CSLASH62 datasheet(157/615 Pages) RENESAS

157 / 615 page

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register

1-138

Function

Normal mode

I2C mode (Note 1)

Factor of interrupt number 15 (Note 2)

UART2 transmission

No acknowledgment detection (NACK)

Factor of interrupt number 16 (Note 2)

UART2 reception

Start condition detection or stop

condition detection

UART2 transmission output delay

Not delayed

Delayed

P70 at the time when UART2 is in use

TxD2 (output)

SDA (input/output) (Note 3)

P71 at the time when UART2 is in use

RxD2 (input)

SCL (input/output)

P72 at the time when UART2 is in use

CLK2

P72

DMA1 factor at the time when 1 1 0 1 is assigned

to the DMA request factor selection bits

UART2 reception

Acknowledgment detection (ACK)

Noise filter width

15ns

50ns

Reading P71

Reading the terminal when 0 is

assigned to the direction register

Reading the terminal regardless of the

value of the direction register

Note 1: Make the settings given below when I2C mode is in use.

Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register.

Disable the RTS/CTS function. Choose the MSB First function.

Note 2: Follow the steps given below to switch from a factor to another.

1. Disable the interrupt of the corresponding number.

2. Switch from a factor to another.

3. Reset the interrupt request flag of the corresponding number.

4. Set an interrupt level of the corresponding number.

Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.

Factor of interrupt number 10 (Note 2)

Bus collision detection

Acknowledgment detection (ACK)

Initial value of UART2 output

H level (when 0 is assigned to

the CLK polarity select bit)

The value set in latch P70 when the port is

selected

Table 1.16.9. Features in I2C mode

P70/TxD2/SDA

P71/RxD2/SCL

CLK

control

P72/CLK2

Falling edge

detection

UART2 reception/ACK interrupt

request, DMA1 request

To DMA0, DMA1

To DMA0

P70 through P72 conforming to the simplified I C bus

I/O

Timer

UART2

Timer

UART2

IICM=1 (SDDS=0) or

DL=000 (SDDS=1)

IICM=0

or IICM2=1

IICM=1

and IICM2=0

SDHI

Noize

Filter

Timer

UART2

I/O

NACK

ACK

UART2

IICM=1

IICM=0

IICM=1

IICM=0

IICM=1

IICM=0

I/O

ALS

IICM=0 or

≠000 (SDDS=1)

SDDS=0

or DL=000

SDDS=1 and

≠000

SWC2

Falling edge of 9 bit

SWC

IICM=1

and IICM2=0

IICM=0

or IICM2=1

Selector

Noize

Filter

Noize

Filter

With IICM set to 1, the port terminal is to be readable

even if 1 is assigned to P7 1 of the direction register.

Port reading

External clock

Internal clock

9th pulse

Bus collision

detection

Bus collision/start, stop condition

detection interrupt request

UART2 transmission/

NACK interrupt request

Start condition

detection

Stop condition

detection

L-synchronous

output enabling

bit

(Port P71 output data latch)

Data bus

Reception register

Bus busy

Transmission

Arbitration

Analog

delay

Digital delay

(Divider)

Figure 1.16.27. Functional block diagram for I2C mode

M16C/62 bảng dữ liệu(PDF) 157 Page - Renesas Technology Corp

M16C/62 bảng dữ liệu(HTML) 157 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL