7643 datasheet(275/424 Pages) RENESAS

275 / 424 page

Rev.2.00

Aug 28, 2006

page 154 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

Fig. 2.6.49 Connection diagram

UTXD

CTS

General purpose

port 1

General purpose

port 2

P85/URXD

P87/RTS

P41/INT0

P40

7643 Group

Host CPU

Receiving side

Transmitting side

USB

Transfer

USB IN

Host PC

(2)

Application example 2: Data packet transfer from UART to USB FIFO (without DMA)

Outline: The data received from host CPU through UART to the USB FIFO is written, and then

it is transmitted to host PC.

Specification: - Use USB endpoint 1 IN bulk transfer is used.

- USB endpoint 1 IN interrupt is used.

- USB endpoint one packet size: 64 bytes

- UART receive is used.

- UART receive buffer full interrupt is used.

- UART receive summing error interrupt is used.

- Transfer bit rate: 9600bps (

φ= 12MHz divided by 1248)

- Data format: 1ST-8DATA-1SP

- Parity bit is disabled.

- Re-transmit is executed if transfer error occurs (re-transmit in byte unit)

-P40 pin to detect packet transmit from host CPU is used. (the host CPU keeps P40

at “L” during a packet transfer, at “H” at all other times)

- RTS function is used.

When the USB FIFO data is transmitted to the host PC, in the 7643 Group, a USB endpoint 1

interrupt occurs. At this point, the 7643 MCU enables the UART receive (UART receive buffer full

interrupt, UART receive summing error interrupt).

After the UART function is received from the host PC, in the 7643 Group, a UART receive buffer

full interrupt occurs; the UART transmit/receive buffer register is read and the received data is

written to the USB FIFO. The RTS pin is set to “L”, indicating that the RTS pin is ready to receive

the next data. If Port P40 is “H” at this point, that receive of one-packet data (64 bytes or more)

has been completed is recognized, and sets the IN_PKT_RD flag USB endpoint 1 IN. This makes

the data in the USB endpoint 1 FIFO ready for transmit.

On the other hand, if a UART receive summing error interrupt, not the UART receive buffer

interrupt, occurs, both the UART transmit/receive buffer register and the UART status register is

read (this clears the error flag), and an “L” pulse is generated to P41 (as a result from this

operation, the re-transmit the previous data from the host CPU is realized). Note that the data

received when an error occurs will be erased.

Figure 2.6.49 shows the connection diagram, Figures 2.6.50 to 2.6.53 show related register settings,

and Figures 2.6.54 and 2.6.55 show control procedure examples.

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