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7643 bảng dữ liệu(PDF) 204 Page - Renesas Technology Corp |
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7643 bảng dữ liệu(HTML) 204 Page - Renesas Technology Corp |
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204 / 424 page  Rev.2.00 Aug 28, 2006 page 83 of 202 7643 Group REJ09B0133-0200 APPLICATION 2.5 DMAC Fig. 2.5.9 Structure of Interrupt request register A Interrupt request register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register A (IREQA : address 0216) b 0 1 2 3 4 5 6 7 Name 0 Functions At reset R W 0 0 0 0 0 0 USB function interrupt request bit INT1 interrupt request bit DMAC0 interrupt request bit UART receive buffer full interrupt request bit INT0 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued DMAC1 interrupt request bit UART transmit interrupt request bit 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽: “0” can be set by software, but “1” cannot be set. Nothing is arranged for this bit. When this bit is read out, the contents are undefined. This bit is “0” at write. Interrupt control register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register A (ICONA : address 0516) b 0 0 1 2 3 4 5 6 7 Name 0 Functions At reset R W 0 0 0 0 0 0 USB function interrupt enable bit INT1 interrupt enable bit DMAC0 interrupt enable bit UART receive buffer full interrupt enable bit INT0 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled DMAC1 interrupt enable bit UART transmit interrupt enable bit 0 Nothing is arranged for this bit. Fix this bit to “0”. Fig. 2.5.10 Structure of Interrupt control register A |
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