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7643 bảng dữ liệu(PDF) 126 Page - Renesas Technology Corp |
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7643 bảng dữ liệu(HTML) 126 Page - Renesas Technology Corp |
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126 / 424 page ![]() Rev.2.00 Aug 28, 2006 page 5 of 202 7643 Group REJ09B0133-0200 APPLICATION 2.1 I/O Port Fig. 2.1.6 Structure of Port control register Port control register b7 b6 b5 b4 b3 b2 b1 b0 Port control register (PTC : address 1016) b 0 0 1 2 4 Name 0 Functions At reset R W 0 0 0 0 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 5 0 0 : Disabled 1 : Enabled 6 0 Port P2 input level select bit 0 : Reduced VIHL level input (Note 2) 1 : CMOS level input 7 0 Port P0 to P3 slew rate control bit (Note 1) Port P4 slew rate control bit (Note 1) Port P5 slew rate control bit (Note 1) Port P6 slew rate control bit (Note 1) Port P7 slew rate control bit (Note 1) Port P8 slew rate control bit (Note 1) 3 Notes 1: The slew rate function can reduce di/dt by modifying an internal buffer structure. 2: The characteristics of VIHL level is basically the same as that of TTL level. But, its switching center point is a little higher than TTL’s. Nothing is arranged for this bit. Fix this bit to “0”. Fig. 2.1.7 Structure of Port P2 pull-up control register Port P2 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P2 pull-upt control register (PUP2 : address 1216) b 0 1 2 4 Name 0 Functions At reset R W 0 0 0 0 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 5 0 0 : Disabled 1 : Enabled 6 0 Port P26 pull-up control bit 0 : Disabled 1 : Enabled 7 0 Port P27 pull-up control bit 0 : Disabled 1 : Enabled Port P20 pull-up control bit Port P21 pull-up control bit Port P22 pull-up control bit Port P23 pull-up control bit Port P24 pull-up control bit Port P25 pull-up control bit 3 |
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