HD64F2149YV datasheet(297/1075 Pages) RENESAS

297 / 1075 page

Section 8 I/O Ports

Rev. 3.00 Jan 18, 2006 page 269 of 1044

REJ09B0280-0300

PCDDR and PDDDR are initialized to H'00 by a reset and in hardware standby mode. They retain

their prior states in software standby mode.

Port C and port D Output Data Registers (PCODR, PDODR)

Bit

6543

210

PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR

Initial value

0000

000

Read/Write

R/W

Bit

6543

210

PD7ODR PD6ODR PD5ODR PD4ODR PD3ODR PD2ODR PD1ODR PD0ODR

Initial value

0000

000

Read/Write

R/W

PCODR and PDODR are 8-bit read/write registers that store output data for the pins on ports C

and D (PC7 to PC0 and PD7 to PD0). PCODR and PDODR can always be read from or written to,

regardless of the PCDDR and PDDDR settings.

PCODR and PDODR are initialized to H'00 by a reset and in hardware standby mode. They retain

their prior states in software standby mode.

Port C and port D Input Data Registers (PCPIN, PDPIN)

Bit

6543

210

PC7PIN

PC6PIN

PC5PIN

PC4PIN

PC3PIN

PC2PIN

PC1PIN

PC0PIN

Initial value

—*

Read/Write

RRRR

RRR

Note:

Determined by the state of pins PC7 to PC0.

Bit

6543

210

PD7PIN

PD6PIN

PD5PIN

PD4PIN

PD3PIN

PD2PIN

PD1PIN

PD0PIN

Initial value

—*

Read/Write

RRRR

RRR

Note:

Determined by the state of pins PD7 to PD0.

Reading PCPIN and PDPIN always returns the pin states.

HD64F2149YV bảng dữ liệu(PDF) 297 Page - Renesas Technology Corp

HD64F2149YV bảng dữ liệu(HTML) 297 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL