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HD64F2149YV bảng dữ liệu(PDF) 273 Page - Renesas Technology Corp

tên linh kiện HD64F2149YV
Giải thích chi tiết về linh kiện  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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HD64F2149YV bảng dữ liệu(HTML) 273 Page - Renesas Technology Corp

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Section 8 I/O Ports
Rev. 3.00 Jan 18, 2006 page 245 of 1044
REJ09B0280-0300
When the ABW bit in WSCR is cleared to 0, pin P90 becomes a bus control output (
LWR),
regardless of the input/output direction indicated by P90DDR. When the ABW bit is 1, pin P90
becomes an output port if P90DDR is set to 1, and an input port if P90DDR is cleared to 0.
• Modes 2 and 3 (EXPE = 0)
When the corresponding P9DDR bits are set to 1, pin P96 functions as the
φ output pin and
pins P97 and P95 to P90 become output ports. When P9DDR bits are cleared to 0, the
corresponding pins become input ports.
Port 9 Data Register (P9DR)
Bit
765
432
10
P97DR
P96DR
P95DR
P94DR
P93DR
P92DR
P91DR
P90DR
Initial value
0
—*
0
000
00
Read/Write
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Note:
*
Determined by the state of pin P96.
P9DR is an 8-bit readable/writable register that stores output data for the port 9 pins (P97 to P90).
With the exception of P96, if a port 9 read is performed while P9DDR bits are set to 1, the P9DR
values are read directly, regardless of the actual pin states. If a port 9 read is performed while
P9DDR bits are cleared to 0, the pin states are read.
P9DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.



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