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HD64F2149YV bảng dữ liệu(PDF) 255 Page - Renesas Technology Corp |
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HD64F2149YV bảng dữ liệu(HTML) 255 Page - Renesas Technology Corp |
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255 / 1075 page  Section 8 I/O Ports Rev. 3.00 Jan 18, 2006 page 227 of 1044 REJ09B0280-0300 Port 5 Data Direction Register (P5DDR) 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 0 P50DDR 0 W 2 P52DDR 0 W 1 P51DDR 0 W Bit Initial value Read/Write P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be returned. Bits 7 to 3 are reserved. Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P5DDR is initialized to H'F8 by a reset and in hardware standby mode. It retains its prior state in software standby mode. As SCI0 is initialized, the pin states are determined by the IIC0 ICCR, P5DDR, and P5DR specifications. Port 5 Data Register (P5DR) 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 0 P50DR 0 R/W 2 P52DR 0 R/W 1 P51DR 0 R/W Bit Initial value Read/Write P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P52 to P50). If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly, regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read. Bits 7 to 3 are reserved; they cannot be modified and are always read as 1. P5DR is initialized to H'F8 by a reset and in hardware standby mode. It retains its prior state in software standby mode. |
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