HD64F2149YV datasheet(202/1075 Pages) RENESAS

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Section 7 Data Transfer Controller

Rev. 3.00 Jan 18, 2006 page 174 of 1044

REJ09B0280-0300

7.2.5

DTC Transfer Count Register A (CRA)

76543210

CRAH

CRAL

Bit

Initial value

—

Unde-

fined

Read/Write

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA register functions as a 16-bit transfer counter (1 to 65,536). It is

decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.

In repeat mode or block transfer mode, CRA is divided into two parts: the upper 8 bits (CRAH)

and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-

bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the

contents of CRAH are transferred when the count reaches H'00. This operation is repeated.

7.2.6

DTC Transfer Count Register B (CRB)

76543210

Bit

Initial value

—

——

—

——

—

——

—

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Read/Write

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in

block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1

every time data is transferred, and transfer ends when the count reaches H'0000.

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