HD64F2149YV datasheet(193/1075 Pages) RENESAS

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Section 6 Bus Controller

Rev. 3.00 Jan 18, 2006 page 165 of 1044

REJ09B0280-0300

6.7

Bus Arbitration

6.7.1

Overview

The H8S/2169 or H8S/2149 has a bus arbiter that arbitrates bus master operations.

There are two bus masters, the CPU and the DTC, which perform read/write operations when they

have possession of the bus. Each bus master requests the bus by means of a bus request signal. The

bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a

bus request acknowledge signal. The selected bus master then takes possession of the bus and

begins its operation.

6.7.2

Operation

The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus

request acknowledge signal to the bus master making the request. If there are bus requests from

both bus masters, the bus request acknowledge signal is sent to the one with the higher priority.

When a bus master receives the bus request acknowledge signal, it takes possession of the bus

until that signal is canceled.

The order of priority of the bus masters is as follows:

(High)

DTC

CPU

(Low)

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